Case Number: 25MST008
Manager: Robert Prosak
Director, IP & Licensing
S&T Technology Transfer & Economic Development
robert.prosak@mst.edu
PDF Download: Automated Optimization Of Decoupling Capacitor Layout Marketing Slick
Publication: Automated Optimization Of Decoupling Capacitor Layout Publication

Opportunity

Seeking a licensing and development partner to bring this decoupling capacitor design software to market.

Problem Statement

Modern SoCs split power across many domains to manage energy use and performance. Each domain needs decoupling capacitors placed correctly to keep power delivery stable and noise-free. Engineers currently place these capacitors by hand through trial and error. That works fine on simple boards. It breaks down quickly as the number of power domains grows and impedance targets tighten. Existing commercial tools cannot handle this many variables at once during the pre-layout stage. The result is suboptimal capacitor layouts, more design cycles, and higher cost.

Solution

Researchers at Missouri University of Science and Technology built a software tool that automates pre-layout decoupling capacitor placement for boards with any number of power domains. The tool treats each power pin as its own learning agent. These agents use multi-agent reinforcement learning to try different capacitor sizes and orientations until they reach a layout with no physical overlaps. A genetic algorithm then removes capacitors while checking impedance against each domain’s target. It stops once it reaches the smallest set of capacitors that still meets every target. The whole process runs on a standard laptop with no external simulation tools required.

Value Proposition

The tool turns a job that normally takes engineers hours or days into minutes. In one test case, it solved four power domains with different target impedances in about five minutes and cut the needed capacitor count from 28 down to 17 while meeting every target. On a real 21-domain SoC used in a mobile device, it delivered a complete optimized layout in 30 minutes. It also automatically shifts more capacitors to the domains with the tightest impedance requirements, a judgment call engineers usually only get right after several rounds of manual tuning.

Development Stage

Software developed in house and validated through simulation on a four domain test board and a real 21 domain mobile SoC design.

Intellectual Property

Utility Patent Application Filed

Inventors

Haran Manoharan, PhD and Chulsoon Hwang, PhD